i) Field of the Invention
The present invention relates to an inspection method for a layout pattern of a logic circuit device or the like and a logical simulator for implementing the same.
ii) Description of the Related Arts
Generally, when designing the layout of a logic integrated circuit device, an unpredictable or unexpected electrostatic capacitance, that is, a parasitic capacitance is often caused. Because of the influence of this parasitic capacitance, the delay of a gate is increased to sometimes cause a malfunction in a completed product. In order to prevent the occurrence of this malfunction, conventionally, the wiring having a particularly large delay time influence on a circuit is marked and listed in advance. When the layout of the logic integrated circuit is manually designed, in particular, it is considered that the listed wiring is connected so as to be as short as possible in order to reduce the parasitic capacitance. In the automatic layout designing of the logic integrated circuit, a limitation is given to the wiring length by using various parameters.
However, since load capacitance differs depending on the types of output gate connected to the wiring, in theory, it is necessary to change the limiting extent of the wiring length for each type of output gate, but this is hardly practical. Further, control of the relative delay time is a very difficult task.
On the other hand, software for extracting the parasitic capacitance of the wiring after finishing the layout design of the logic integrated circuit is already available. Thus, it is possible to calculate the parasitic capacitance of the wiring by using this software, but there are no means for making efficient use of this calculated parasitic capacitance value. As a result, much effort is required for the feedback of the parasitic capacitance to the layout design stage.
Hence, the present inventor has proposed an inspection method for a layout pattern of a logic integrated circuit device or the like, which is capable of not only setting various limitations on the layout design but also predicting any malfunction of the completed product due to the delay time after finishing the layout design. In this method, a plurality of model values of load capacitance are given to a reference gate by a circuit simulator to calculate corresponding delay times. Then, a function of the load capacitance vs. the delay time is generated from the given model values of the load capacitance and the calculated delay times, and the parasitic capacitance of the layout pattern to be inspected is extracted at the same time. Next, the function of the load capacitance vs. the delay time is made by reference to the wiring of each drive gate and the obtained parasitic capacitance to calculate The delay time at the reference gate. Then, a correction is added to the calculated delay time by considering a wiring logic W/L of the drive gate, and the corrected delay time is transformed to data adaptable to an input format to a logical simulator (analog simulator) for operating the logical simulator. As a result, the comparison between the expected output value of the layout in which the influence of the parasitic capacitance has been corrected and the expected output value of layout at the initial design stage is made possible.
In the above-described conventional layout pattern inspection method, the design margin including the circuit design and the layout design of the products can be exactly predicted. Further, since the design evaluation of the layout pattern can be exactly performed, if there is a problem, the feedback of the result is immediate so no actual product is produced. As a result, the period from the initial design stage to product shipping can be greatly reduced compared with the former method.
However, in this case, for example, delay times of gates G1, G2 and G3 shown in FIG. 8 are dealt with the same value. Even if the wiring length to input terminals of the gates G1, G2 and G3 is equal, the actual delay times are different because of the influence of their line resistances, and thus this method brings about an inspection error. In addition, when the parameter of the logical simulator is changed, each time, it is necessary to recompute the function of the load capacitance vs. the delay time.